This patent application claims priority based on a Japanese patent application, H11-184470 filed on Jun. 29, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a pattern generator and an electric part testing apparatus which generates a test pattern used for testing an electric part.
2. Description of the Related Art
Conventionally, an electric part testing apparatus used for testing an electric part such as semiconductor memory comprises a pattern generator, which generates a test pattern used for testing an electric part. FIG. 1 shows a configuration of a conventional pattern generator. A pattern generator 100 generates a test pattern for a dynamic random access memory (DRAM), which is an example of an electric part.
A pattern generator 100 has a vector memory 102, a read out controller 103, a vector cache memory 104, an address expansion unit 106, an address designating unit (AP) 108, a timer 110, an interruption controller 112, a refresh address-designating unit (SPI) 114, a multiplexer (MUX) 116, and a pattern-generating unit 118. A timer 110 generates an interruption request for every predetermined time interval. The interruption controller 112 sets a refresh cycle signal (REF CYCLE) to xe2x80x9c1xe2x80x9d and outputs to an address expansion unit 106 and a multiplexer 116 on receipt of the interruption request from the timer 110.
The vector memory 102 is constituted by a mass storage static random access memory, SRAM, and stores a vector instruction (sequence instruction) that defines an order for reading out a control instruction, which defines a test pattern to be generated.
The read out controller 103 inputs a part of the vector instruction from the vector memory 102 and outputs the input vector instruction to the vector cache memory 104. The vector cache memory 104 is constituted by a small storage high speed SRAM, and stores a vector instruction input from the read out controller 103. Furthermore, the vector cache memory 104 outputs the vector instruction to the address expansion unit 106 based on the address, which is input from the address-designating unit 108.
The address expansion unit 106 generates an address by interpreting the vector instruction input from the vector cache memory 104 and outputs the generated address to the address-designating unit 108. Moreover, the address expansion unit 106 interrupts the generation of the address when the refresh cycle signal, which is set to xe2x80x9c1xe2x80x9d, is input from the interruption controller 112. The address expansion unit 106 restarts the generation of the address when the refresh cycle signal, which is set to xe2x80x9c0xe2x80x9d, is input from the interruption controller 112. The address-designating unit 108 stores and outputs the address input from the address expansion unit 106.
The refresh address-designating unit 114 stores and outputs an address, which corresponds to the control instruction for refreshing an electric part. The multiplexer 116 selects either the address input from the interruption controller 112 or the address input from the refresh address-designating unit 114, based on the refresh cycle signal input from the interruption controller 112. The address input from the refresh address-designating unit 114 is selected when the refresh cycle is xe2x80x9c1xe2x80x9d, and the address input from the address-designating unit 108 is selected when the refresh cycle signal is xe2x80x9c0xe2x80x9d.
The pattern-generating unit 118 has a control instruction memory 120, pattern operator 122, a resistor XB, a resistor YB, and a resistor RF. The control instruction memory 120 stores a control instruction, which generates a test pattern, and outputs the control instruction corresponding to the address, which is input from the multiplexer 116, to pattern operator 122. The resistor XB stores a value to be provided as a column address of a DRAM, which is an object to be tested. The resistor YB stores a value to be provided as a row address of the DRAM, and the resistor RF stores a row address for refreshing the DRAM. The pattern operator 122 generates a test pattern based on the control instruction output from the control instruction memory 120. Example of test patterns include, an address signal, a Row Address Strobe (RAS) signal, a Column Address Strobe (CAS) signal, a data signal, and a write enable (/WE: where xe2x80x9c/xe2x80x9d stands for reverse logic) signal.
FIG. 2 shows various kinds of information stored in the conventional pattern generator. FIG. 2(A) shows an address stored in the refresh address-designating unit 114. The refresh address-designating unit 114 stores xe2x80x9c1#300xe2x80x9d as an address corresponding to the refresh controlling instruction. FIG. 2(B) shows a sequence instruction stored in the vector memory 102. In FIG. 2(B), xe2x80x9cNOPxe2x80x9d is an instruction that outputs the present address value and advances the address value to the next value, that is, adds xe2x80x9c1xe2x80x9d to the present address value. xe2x80x9cJNI STOxe2x80x9d is an instruction that outputs the present address value and executes the instruction of the address, which is allotted a label STO.
FIG. 2(C) shows a part of a control instruction stored in the control-instruction memory 118. In FIG. 2(C), xe2x80x9cXB less than 0xe2x80x9d is an instruction that clears the value of the resistor XB to xe2x80x9c0xe2x80x9d in the next cycle. xe2x80x9cXB less than XB+1xe2x80x9d is an instruction that adds xe2x80x9c1xe2x80x9d to the value of the resistor XB in the next cycle. xe2x80x9cYB less than 0xe2x80x9d is an instruction that clears the value of the resistor YB to xe2x80x9c0xe2x80x9d in the next cycle. xe2x80x9cYB less than YB+1xe2x80x9d is an instruction that adds xe2x80x9c1xe2x80x9d to the value of the resistor YB in the next cycle. xe2x80x9cRF less than RF+1xe2x80x9d is an instruction that adds xe2x80x9c1xe2x80x9d to the value of the resistor RF in the next cycle.
xe2x80x9cPAGE-INxe2x80x9d is an instruction that outputs a signal to the DRAM for inputting a row address and a column address, which executes the data writing process or data reading process. For example, xe2x80x9cPAGE-INxe2x80x9d is an instruction that outputs the value of the resistor YB as an address signal and outputs a RAS signal, which is set to LOW, and also outputs the value of the resistor XB as an address signal and outputs the CAS signal, which is set to a negative pulse. xe2x80x9cPAGExe2x80x9d is an instruction that outputs the signal to the DRAM for changing a column address, which executes the data writing process or data reading process. For example, xe2x80x9cPAGExe2x80x9d is an instruction that outputs the value of the resistor as an address signal and outputs the CAS signal, which is set to a negative pulse.
xe2x80x9cPAGE-OUTxe2x80x9d is an instruction that outputs a signal to the DRAM for terminating the data reading process or data writing process. For example, xe2x80x9cPAGE-OUTxe2x80x9d is an instruction that outputs the value of the resistor XB as an address signal, and a CAS signal which is set to a negative pulse, and also outputs the RAS signal, which is set to HIGH. By setting the RAS signal to HIGH, the DRAM is pre-charged. That is, the wiring capacity of the DRAM is charged. xe2x80x9cREFRESHxe2x80x9d is an instruction that outputs a signal for executing the refreshing operation on the DRAM. For example, xe2x80x9cREFRESHxe2x80x9d is an instruction that outputs the value of the resistor RF as an address signal and outputs a RAS signal, which is set to LOW.
FIG. 3 shows an operation of the conventional pattern generator. FIG. 3 shows an operation of the pattern generator 100 when the several kinds of information shown in FIG. 2 are stored in the pattern generator. FIG. 3(A) shows a value of an address output from the address-designating unit 108, a value of the address PC output from the multiplexer 116, the value of the resistor XB, the value of the resistor YB, the value of the resistor RF, the value of the refresh cycle (REFCYCLE), the operation of the resistor, which is a provider of the address output to the DRAM, and the operation of the DRAM for each cycle during the operation of the pattern generator. FIG. 3(B) shows a signal, which is output to the DRAM from the pattern generator, from the cycle 6 to cycle 11.
In the cycle 1, the address expansion unit 106 picks out xe2x80x9cNOPxe2x80x9d from the vector cache memory 104, directs the address-designating unit 108 to output the present address value xe2x80x9c#0xe2x80x9d, and sets the address value to xe2x80x9c#1xe2x80x9d. Here, the refresh cycle signal xe2x80x9c#0xe2x80x9d is output from the interruption controller 112. The multiplexer 116 outputs xe2x80x9c#0xe2x80x9d, which is output from the address-designating unit 108, as an address PC to the pattern-generating unit 118 because the refresh cycle signal is xe2x80x9c0xe2x80x9d. Thereby the instruction xe2x80x9cXB less than 0xe2x80x9d, xe2x80x9cYB less than 0xe2x80x9dis output to the pattern operator 122 from the control instruction memory 120. Therefore, the pattern operator 122 sets the values of the resistor XB and the resistor YB to xe2x80x9c0xe2x80x9d in the next cycle.
In the cycle 2, the address expansion unit 106 picks out xe2x80x9cNOPxe2x80x9d from the vector cache memory 104, directs the address-designating unit 108 to output the present address value xe2x80x9c#1xe2x80x9d, and sets the address value to xe2x80x9c#2xe2x80x9d. Here, the refresh cycle signal of xe2x80x9c0xe2x80x9d is output from the interruption controller 112. The multiplexer 116 outputs xe2x80x9c#1xe2x80x9d, which is output from the address-designating unit 108, as an address PC to the pattern-generating unit 118 because the refresh cycle signal is xe2x80x9c0xe2x80x9d. Thereby the instruction xe2x80x9cXB less than XB+1xe2x80x9d, xe2x80x9cPAGE-INxe2x80x9d is output to the pattern operator 122 from the control instruction memory 120.
The pattern operator 122 outputs the value of the resistor YB as an address signal, and the RAS signal which is set to LOW, and then outputs the value of the resistor XB as an address signal, and the CAS signal, which is set to a negative pulse. The DRAM thereby executes the PAGE-IN operation. Moreover, the pattern operator 122 adds xe2x80x9c1xe2x80x9d onto the value of the resistor XB in the next cycle. The same operations shown above are executed from the cycle 3 to cycle 9.
For example, as shown in FIG. 3(B), in the cycle 6, the pattern operator 122 outputs the value of the resistor YB as an address signal and outputs the RAS signal, which is set to LOW., The pattern operator 122 then outputs the value of the resistor XB as an address signal and outputs the CAS signal, which is set to be a negative pulse. The DRAM thereby executes the PAGE-IN operation, that is, the writing process or the reading process of the memory cell corresponding to the column of the value of the resistor XB and the row of the value of the resistor YB.
As shown in FIG. 3(B), in the cycle 7, the pattern operator 122 outputs the value of the resistor XB as an address signal and outputs the CAS signal, which is set to be a negative pulse. The DRAM thereby executes the PAGE operation, that is, the writing process or the reading process of the memory cell corresponding to the column of the value of the resistor XB and the row of the value of the resistor YB, which is input in the cycle 6. The cycle 8 also executes the same operation as shown above.
In the cycle 9, the pattern operator 122 outputs the value of the resistor XB as an address signal, the CAS signal, which is set to be a negative pulse, and then the RAS signal, which is set to HIGH. The DRAM thereby executes the PAGE-OUT operation, that is, the writing process or the reading process of the memory cell corresponding to the column of the value of the resistor XB and the row of the value of the resistor YB, which is input in the cycle 6. The DRAM is thereby pre-charged.
Here, if the timer 110 detects the passing of the predetermined time at the cycle 9, the time for executing the refreshing operation is indicated, and therefore the timer 110 outputs the interruption request to the interruption controller 112. The interruption controller 112 sets the refresh cycle signal to xe2x80x9c1xe2x80x9d and outputs the refresh cycle signal to the address expansion unit 106 and the multiplexer 116 in the next cycle 10.
In the cycle 10, because the refresh cycle signal is xe2x80x9c1xe2x80x9d, the address expansion unit 106 makes the address-designating unit 108 hold the present address value and stops the generation of an address generated by the vector instruction. Furthermore, because the refresh cycle signal is xe2x80x9c1xe2x80x9d, the multiplexer 116 outputs the address xe2x80x9c1#300xe2x80x9d, which is output from the refresh address-designating unit (SPI) 114, to the pattern-generating unit 118 as an address PC.
Thereby, the control instruction memory 120 inputs xe2x80x9cRF less than RF+1xe2x80x9d and xe2x80x9cREFRESHxe2x80x9d to the pattern operator 122. Additionally, as shown in FIG. 3, the pattern operator 122 outputs the value of the resistor RF as an address signal and outputs the RAS signal, which is set to LOW. As a result, the DRAM executes the REFRESH operation, that is, refreshing the row value of the resistor RF. Furthermore, the interruption controller 112 changes the row address, which is to be refreshed in the next cycle, by adding xe2x80x9c1xe2x80x9d onto the value of the resistor RF in the next cycle 11.
In the cycle 11, the interruption controller 112 sets the refresh cycle signal to xe2x80x9c0xe2x80x9d and outputs the refresh cycle signal to the address expansion unit 106 and the multiplexer 116. The address expansion unit 106 thereby restarts the generation of the address by the vector instruction. Moreover, the multiplexer 116 outputs the address, which is output from the address-designating unit 108, to the pattern-generating unit 118 as an address PC. Then the control instruction memory 120 provides to the pattern operator 122, the control instruction-corresponding to the address provided from the multiplexer 116. The pattern operator 122 generates the test pattern according to the control instruction. The following cycles are executed as shown above.
The conventional electric part testing apparatus can perform predetermined testing of an electric part as expected, when the interruption request is generated by the timer 110 at the cycle of the PAGE-OUT, for example, cycle 9. However, because the interruption request generated by the timer 110 is a synchronous with the testing of the electric part, the interruption request may be generated during the cycle of the PAGE-IN and the cycle of the PAGE. Therefore, problems, which hinder the testing, may occur. For example, the refreshing operation may be executed without pre-charging the electric part, and thus the writing process or the reading process cannot be executed properly after the refreshing operation during the testing of the electric part.
Furthermore, in a case of making subroutine a set of a plurality of instructions executed repeatedly, there is a problem where it is difficult to control when and how this subroutine is read from the vector memory 102 to the cache. Also there is a problem where the configuration of the pattern generator becomes complicated in order to solve the above problem. Furthermore, it is difficult to generate a test pattern, which is to be provided to each of the configuration, cooperatively when the pattern generator generates the pattern for testing the device, on which a memory and a logic are mounted together. Even if the pattern can be generated cooperatively, the configuration of the pattern generator becomes complicated.
Therefore, it is an object of the present invention to provide a pattern generator and an electric part testing apparatus which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, a pattern generator that generates a test pattern used for testing an electric part can be provided. The pattern generator may comprise: a pattern memory that stores test pattern information, which defines the test pattern; a vector memory that stores a vector instruction, which indicates an order for reading out the test pattern information from the pattern memory; an address expansion unit that generates an address of the test pattern information in the pattern memory according to the vector instruction stored in the vector memory; an interruption pattern memory that stores interruption test pattern information, which defines the test pattern during a predetermined interruption process; an interruption vector memory, which is different from the vector memory, that stores an interruption vector instruction which indicates an order for reading out the interruption test pattern information from the interruption pattern memory; an interruption address expansion unit that generates an address of the interruption test pattern information according to the interruption vector instruction stored in the interruption vector memory; and a pattern generating unit that generates the test pattern based on the test pattern information corresponding to the address generated by the address expansion unit or the interruption test pattern information corresponding to the address generated by the interruption address expansion unit.
The pattern generator may further comprises: an interruption detecting unit that detects a point in time for starting the interruption process; and the interruption address expansion unit generates the address of the interruption test pattern information based on detection of the point in time for starting the interruption process by the interruption detecting unit; and the pattern generating unit generates the test pattern based on the test pattern information corresponding to the address generated by the address expansion unit when the interruption detecting unit does not detect the point in time for starting the interruption process, and the pattern generating unit generates the test pattern based on the interruption test pattern information corresponding to the address generated by the interruption address expansion unit when the interruption detecting unit detects the point in time for starting the interruption process.
The pattern generator may further comprises: an interruption controller that interrupts generation of the address generated by the address expansion unit based on detection of the point in time for starting the interruption process by the interruption detecting unit; an interruption end detecting unit that detects an end of the interruption process; and a starting controller that starts generation of the address by the address expansion unit based on detection of the end of the interruption process by the interruption end detecting unit.
The electric part may be a memory having a function of storing data and which requires refreshing in order to hold the data, and the interruption pattern memory may store the interruption test pattern information, which defines a test pattern for refreshing the memory. The interruption pattern memory may further store the interruption test pattern information that defines a test pattern for pre-charging the memory and a test pattern for providing a column address, which is provided to the memory before executing the interruption process, to the memory; the pattern generating unit may generate the test pattern in an order of: the test pattern for pre-charging the memory, the test pattern for refreshing the memory, and the test pattern for providing the column address when the interruption detecting unit detects the point in time for starting the interruption process.
The pattern generator may further comprise a timer for measuring time, and the interruption detecting unit detects the point in time for starting the interruption process based on the time measured by the timer. The vector instruction, which is stored in the vector memory, may include a description that indicates the point in time for starting the interruption process; and the interruption detecting unit detects the point in time for starting the interruption process based on the description. Each of the test pattern information and the interruption test pattern may be the test pattern, or a control instruction for generating the test pattern. One of the test pattern information and the interruption test pattern information may be the test pattern; and another thereof may be a control instruction for generating the test pattern.
The test pattern information and the interruption test pattern information may be stored on a single memory space corresponding to the addresses which are different from each other; and the pattern generating unit may include: an address selecting unit that selects the address generated by the address expansion unit when the interruption detecting unit does not detect the point in time for starting the interruption process and selects the address generated by the interruption address expansion unit when the interruption detecting unit detects the point in time for starting the interruption process; and a unified pattern generating unit that generates the test pattern based on the test pattern information or the interruption test pattern information corresponding to the address selected by the address selecting unit.
The pattern generator may include: a first pattern generating unit that generates the test pattern based on the test pattern information corresponding to the address generated by the address expansion unit; a second pattern generating unit that generates the test pattern based on the interruption test pattern corresponding to the address generated by the interruption address expansion unit; and a test pattern selecting unit that selects the test pattern generated by the first pattern generating unit when the interruption detecting unit does not detect the point in time for starting the interruption process, and selects the test pattern generated by the second pattern generating unit when the interruption detecting-unit detects the point in time for starting the interruption process.
According to the second aspect of the present invention, an electric part testing apparatus for testing an electric part can be provided. The electric part testing apparatus may comprise: a pattern memory that stores test pattern information that defines a test pattern including an input test pattern provided to the electric part for the testing, and an expected value, which is expected to be output from the electric part after providing the input test pattern to the electric part; a vector memory that stores a vector instruction, which indicates an order for reading out the test pattern information from the pattern memory; an address expansion unit that generates an address of the best pattern information in the pattern memory according to the vector instruction stored in the vector memory; an interruption pattern memory that stores interruption test pattern information, which defines the test pattern during a predetermined interruption process; an interruption vector memory that stores an interruption vector instruction, which indicates an order for reading out the interruption test pattern information from the interruption pattern memory; an interruption address expansion unit that generates an address of the interruption test pattern information in the interruption pattern memory according to the interruption vector instruction stored in the interruption vector memory; a pattern generating unit that generates the test pattern based on the test pattern information corresponding to the address generated by the address expansion unit or the interruption test pattern information corresponding to the address generated by the interruption address expansion unit; a pin data selector that rearranges the test pattern generated by the pattern generating unit according to a pin arrangement of electric terminals of the electric part; a waveform formatter that formats a waveform of the input test pattern, which is included in the test pattern output from the pin data selector; a device socket that provides the input test pattern formatted by the waveform formatter to the electric part and receives an output signal output from the electric part; and a comparator that compares the output signal, which is received by the device socket, with the expected value.
The electric part testing apparatus may further comprise: an interruption detecting unit that detects a point in time for starting the interruption process; and the interruption address expansion unit generates the address of the interruption test pattern information based on detection of the point in time for starting the interruption process by the interruption detecting unit; and the pattern generating unit generates the best pattern based on the test pattern information corresponding to the address generated by the address expansion unit when the interruption detecting unit does not detect the point in time for starting the interruption process, and the pattern generating unit generates the test pattern based on the interruption test pattern information corresponding to the address generated by the interruption address expansion unit when the interruption detecting unit detects the point in time for starting the interruption process.
The electric part testing apparatus may further comprise: an interruption controller that interrupts generation of the address generated by the address expansion unit based on detection of the point in time for starting the interruption process by the interruption detecting unit; an interruption end detecting unit that detects an end of the interruption process; and a starting controller that starts generation of the address by the address expansion unit based on detection of the end of the interruption process by the interruption end detecting unit.
The electric part may be a memory having a function of storing data and which requires refreshing in order to hold the data, and the interruption pattern memory stores the interruption test pattern information, which defines a test pattern for refreshing the memory. The interruption pattern memory may further store the interruption test pattern information that defines a test pattern for pre-charging the memory and a test pattern for providing a column address, which is provided to the memory before executing the interruption process, to the memory; the pattern generating unit may generate the test pattern in an order of: the test pattern for pre-charging the memory, the test pattern for refreshing the memory, and the test pattern for providing the column address to the memory when the interruption detecting unit detects the point in time for starting the interruption process.
According to the third aspect of the present invention, a method for generating a test pattern used for testing an electric part can be provided. The method may include: generating test pattern information, which defines the test pattern; generating a vector instruction, which indicates an order for reading out the test pattern information; generating an address of the test pattern information according to the vector instruction; generating interruption test pattern information, which defines the test pattern during a predetermined interruption process; generating an interruption vector instruction, which indicates an order for reading out the interruption test pattern information; generating an address of the interruption test pattern information according to the interruption vector instruction; and generating the test pattern based on the test pattern information corresponding to the address generated by the generating the address of the test pattern information or the interruption test pattern information corresponding to the address generated by the generating the address of the interruption test pattern information.
This summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the above described features. The above and other features and advantages of the present invention will become more apparent from the following description of embodiments taken in conjunction with the accompanying drawings.